(1) Field of the Invention
The present invention relates to semiconductor devices including gate electrodes and dummy gate electrodes and methods for fabricating the same.
(2) Description of Related Art
In recent years, with an increasing degree of integration of semiconductor integrated circuits and an increasing operating speed thereof, increasing significance has been attached to control over the dimensions of gate electrodes of MIS transistors which significantly influence the characteristics of semiconductor integrated circuits. Meanwhile, a part of a semiconductor integrated circuit in which MIS transistors densely exist and a part thereof in which MIS transistors sparsely exist are both necessarily mixed in the semiconductor integrated circuit. Such variations in the density of MIS transistors formed in a semiconductor integrated circuit have an influence on processes for processing gate electrodes of MIS transistors, such as a photolithography process and an etching process, leading to an increase in differences in dimension among processed gate electrodes. After formation of MIS transistors, an interlayer dielectric deposited on the MIS transistors is planarized by chemical mechanical polishing (CMP). The thickness of the planarized interlayer dielectric significantly depends on the density of transistors located under the interlayer dielectric.
In order to solve the above-described problem, the following method has been suggested: For example, dummy gate electrodes that are unnecessary for actual circuit operation are uniformly formed in a semiconductor device, thereby suppressing the above-described process variations.
FIGS. 6A and 6B are diagrams illustrating a known method for forming a gate electrode. The known method is disclosed in Japanese Unexamined Patent Publication No. 2000-112114. As illustrated in FIGS. 6A and 6B, dummy gate electrodes are formed in the vicinity of gate electrodes. In this way, all the gate electrodes including dummy gate electrodes can be arranged under the same surrounding conditions. This can suppress variations in dimension among gates.
In a case where an interlayer dielectric deposited to cover MIS transistors is to be planarized by CMP, dummy gate electrodes have been widely utilized to make the thickness of the planarized interlayer dielectric uniform, thereby reducing variations in the density of gate electrodes among locations.
On the other hand, in order to further increase the operating speed of semiconductor devices, metals or their alloys have been frequently used which achieve a reduction in the resistance of gate electrodes and contribute to the stability of transistor characteristics. These materials are metallurgically stable toward heat and chemical solutions and of low resistance and high reliability. This significantly contributes to increases in the degree of integration and operating speed of semiconductor integrated circuits. One of the techniques using such a metal is a silicidation technique. In recent years, this silicidation technique has been widely utilized for fabrication of semiconductor devices.